Electronic design automation (EDA) tools are used to design integrated circuits. Integrated circuits can include many thousands and perhaps millions of circuit elements (e.g., transistors, logic gates, diodes, etc.) and interconnecting wires and busses. The circuit elements and wires can be formed on many different layers, with various interconnections (e.g., vias) between layers. EDA tools allow a designer to describe an integrated circuit based on its desired behavior, and then transform that behavioral description into a set of geometric shapes called a layout which forms the circuit elements and wires for all the different layers.
As integrated circuit feature sizes continually get smaller and smaller, EDA tools need to be aware of an ever-increasing number of constraints (e.g., design rules or design rule manuals (DRMs)) to ensure that shapes are placed correctly for a target fabrication process. For example, some foundries specify that shapes of a design can only be placed in parallel routing tracks (hereinafter simply “tracks”) running in one direction of a given layer or portion of a layer and these tracks must have minimum spacing requirements (e.g., forbidden pitch). Moreover, to allow a design to be implemented by multiple patterning processes (e.g., double patterning), shapes in adjacent tracks may have alternate colors (e.g., B for shapes to be included in a “blue” photomask, C for shapes to be included in a “cyan” photomask, etc.) and the widths for shapes in adjacent tracks may need to conform to further requirements. Still further, even separate metal shapes within a track must conform to minimum spacing requirements (e.g., line end-to-end spacing).
Some EDA tools such as design rule checkers can be used to assist a designer in identifying and fixing IC designs having design rule violations. However, further automation and assistance for helping a designer with many of these violations is needed.